1. Field of the Invention
This invention relates to the field of microprocessors and, more particularly, to a microprocessor configured to interpret instructions according to one of a pair of instruction sets depending upon the detection of a predefined plurality of instructions. If the predefined plurality of instructions is not detected, instructions are interpreted as being from the first of the pair of instruction sets. If the predefined plurality of instructions is detected, instructions are interpreted as being from the second of the pair of instruction sets.
2. Description of the Relevant Art
Computer systems employ one or more microprocessors, and often employ digital signal processors (DSPs). The DSPs are typically included within multimedia devices such as sound cards, speech recognition cards, video capture cards, etc. The DSPs function as coprocessors, performing complex and repetitive mathematical computations demanded by multimedia devices and other signal processing applications more efficiently than general purpose microprocessors. Microprocessors are typically optimized for performing integer operations upon values stored within a main memory of a computer system. While DSPs perform many of the multimedia functions, the microprocessor manages the operation of the computer system.
Digital signal processors include execution units which comprise one or more arithmetic logic units (ALUs) coupled to hardware multipliers which implement complex mathematical algorithms in a pipelined manner. The instruction set primarily comprises DSP-type instructions (i.e. instructions optimized for the performance of complex mathematical operations) and also includes a small number of non-DSP instructions. The non-DSP instructions are in many ways similar to instructions executed by microprocessors, and are necessary for allowing the DSP to function independent of the microprocessor.
The DSP is typically optimized for mathematical algorithms such as correlation, convolution, finite impulse response (FIR) filters, infinite impulse response (IIR) filters, Fast Fourier Transforms (FFTs), matrix computations, and inner products, among other operations. Implementations of these mathematical algorithms generally comprise long sequences of systematic arithmetic/multiplicative operations. These operations are interrupted on various occasions by decision-type commands. In general, the DSP sequences are a repetition of a very small set of instructions that are executed 70% to 90% of the time. The remaining 10% to 30% of the instructions are primarily boolean/decision operations. Many of these mathematical algorithms perform a repetitive multiply and accumulate function in which a pair of operands are multiplied together and added to a third operand. The third operand is often used to store an accumulation of prior multiplications. Therefore, DSP hardware often includes hardware configured to quickly perform a multiply-add sequence. An exemplary DSP is the ADSP 2171 available from Analog Devices, Inc. of Norwood, Mass.
Many instruction sequences (or "routines") which perform complex mathematical operations may be more efficiently performed in a DSP instruction set such as that employed by the ADSP 2171 than in the x86 instruction set. Microprocessors often execute instructions from the x86 instruction set, due to its widespread acceptance in the computer industry. It is desirable to code the various instruction sequences of a program in the instruction set (DSP or x86, for example) which is most efficient at performing the task the instruction sequence represents. Furthermore, a method is desired for indicating the instruction set in which each instruction sequence in a particular program is coded. As used herein, an "instruction set" refers to a plurality of instructions defined for execution by a particular microprocessor. Each instruction within the instruction set is assigned a unique encoding identifying the instruction from the other instructions within the instruction set.